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1
TC7129 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS
FEATURES
s s s s s s s s s Count Resolution ......................................... 19,999 Resolution on 200 mV Scale .......................... 10 V True Differential Input and Reference Low Power Consumption ................... 500 A at 9V Direct LCD Driver for 4-1/2 Digits, Decimal Points, Low-Battery Indicator, and Continuity Indicator Overrange and Underrange Outputs Range Select Input ............................................ 10:1 High Common-Mode Rejection Ratio ......... 110 dB External Phase Compensation Not Required
2 3 4 5
GENERAL DESCRIPTION
The TC7129 is a 4-1/2 digit analog-to-digital converter (ADC) that directly drives a multiplexed liquid crystal display (LCD). Fabricated in high-performance, low-power CMOS, the TC7129 ADC is designed specifically for highresolution, battery-powered digital multimeter applications. The traditional dual-slope method of A/D conversion has been enhanced with a successive integration technique to produce readings accurate to better than 0.005% of full scale, and resolution down to 10 V per count. The TC7129 includes features important to multimeter applications. It detects and indicates low-battery condition. A continuity output drives an annunciator on the display, and can be used with an external driver to sound an audible alarm. Overrange and underrange outputs and a rangechange input provide the ability to create auto-ranging instruments. For snapshot readings, the TC7129 includes a latch-and-hold input to freeze the present reading. This combination of features makes the TC7129 the ideal choice for full-featured multimeter and digital measurement applications.
ORDERING INFORMATION
Part No.
TC7129CKW TC7129CLW TC7129CPL
Pin Layout
Formed -- Normal
Package
44-Pin PQFP 44-Pin PLCC 40-Pin PDIP
Temperature Range
0C to +70C 0C to +70C 0C to +70C
TYPICAL OPERATING CIRCUIT
LOW BATTERY CONTINUITY
V+ 5 pF
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
6
120 kHz 330 k
TC7129
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
* 0.1 F 1 F 150 k + 9V - 10 k +
0.1 F
10 pF 20 k TC04 0.1 F V+
7
100 k + VIN
* NOTE: RC network between pins 26 and 28 is not required.
TC7129-5 10/18/96
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage to Reference Voltage (REF HI or REF LO) .............. V+ to V- Input Voltage (IN HI or IN LO) (Note 1) ................ V+ to V- VDISP ................................................V+ to (DGND - 0.3V) Digital Input, Pins 1, 2, 19, 20, 21, 22, 27, 37, 39, 40 .......... DGND to V+ Analog Input, Pins 25, 29, 30 ............................... V+ to V- Package Power Dissipation (TA 70C) Plastic DIP ........................................................1.23W PLCC ................................................................1.23W Plastic QFP .......................................................1.00W Operating Temperature Range .................... 0C to +70C (V+ V-) ............................................ 15V Storage Temperature Range ................ - 65C to +150C Lead Temperature (Soldering, 10 sec) ................. +300C
Notes: Input voltages may exceed supply voltages, provided input current is limited to 400 A. Currents above this value may result in invalid display readings but will not destroy the device if limited to 1 mA. Dissipation ratings assume device is mounted with all leads soldered to printed circuit board. *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS: V+ to V- = 9V, VREF = 1V, TA = +25C, fCLK = 120 kHz, unless otherwise
indicated. Pin numbers refer to 40-pin DIP. Symbol
Input Zero Input Reading Zero Reading Drift Ratiometric Reading Range Change Accuracy RE NL CMRR CMVR eN IIN Roll-Over Error Linearity Error Common-Mode Rejection Ratio Common-Mode Voltage Range Noise (Peak-to-Peak Value Not Exceeded 95% of Time) Input Leakage Current Scale Factor Temperature Coefficient Common Voltage Common Sink Current Common Source Current Digital Ground Voltage Sink Current Supply Voltage Range Supply Current Excluding Common Current Clock Frequency VDISP Resistance Low-Battery Flag Activation Voltage Continuity Comparator Threshold Voltages Pull-Down Current
3-232
Parameter
Test Conditions
VIN = 0V, 200 mV Scale VIN = 0V, 0C < TA < +70C VIN = VREF = 1000 mV, Range = 2V VIN = 0.1V on Low Range VIN = 1V on High Range -VIN = +VIN = 199 mV 200 mV Scale VCM = 1V, VIN = 0V, 200 mV Scale VIN = 0V 200 mV Scale VIN = 0V 200 mV Scale VIN = 0V, Pins 32, 33 VIN = 199 mV, 0C < TA < +70C External VREF = 0 ppm/C V+ to Pin 28 Common = +0.1V Common = -0.1V V+ to Pin 36, V+ to V- = 9V DGND = +0.5V V+ to V- V+ to V- = 9V VDISP to V+ V+ to V- VOUT Pin 27 = High VOUT Pin 27 = Low Pins 37, 38, 39
Min
Typ
Max
+0000 -- 10000 1.0001 2 -- -- -- -- -- 10 7
Unit
Counts V/C Counts Ratio Counts Counts dB V V VP-P pA ppm/C
- 0000 0000 -- 0.5 9997 9999 0.9999 1.0000 -- -- -- -- -- -- -- -- 1 1 110 (V-) +1.5 (V+) -1 14 1 2
Power VCOM
DGND
IS fCLK
2.8 -- -- 4.5 -- 6 -- -- -- 6.3 100 -- --
3.2 0.6 10 5.3 1.2 9 0.8 120 50 7.2 200 200 2
3.5 -- -- 5.8 -- 12 1.3 360 -- 7.7 -- 400 10
V mA A V mA V mA kHz k V mV mV A
Digital
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
ELECTRICAL CHARACTERISTICS: V+ to V- = 9V, VREF = 1V, TA = +25C, fCLK = 120 kHz, unless otherwise
indicated. Pin numbers refer to 40-pin DIP. Symbol Parameter
"Weak Output" Current Sink/Source Pin 22 Source Current Pin 22 Sink Current
1
Test Conditions
Pins 20, 21 Sink/Source Pin 27 Sink/Source
Min
-- -- -- --
Typ
3/3 3/9 40 3
Max
-- -- -- --
Unit
A A A A
2 3 4 5
PIN CONFIGURATIONS 40-Pin PDIP
OSC1 OSC3 ANNUNICATOR DRIVE B1, C1, CONT A1, G1, D1 F1, E1, DP1 B2, C2, LO BATT A2, G2, D2 F2, E2, DP2 1 2 3 4 5 6 7 8 9 40 OSC2 39 DP1 38 DP2 37 RANGE 36 DGND 35 REF LO 34 REF HI 33 IN HI 32 31 IN LO
B3, C3, MINUS 10 DISPLAY A3, G3, D3 11 OUTPUT F3, E3, DP3 12 LINES B4, C4, BC5 13 A4, G4, D4 F4, E4, DP4 BP3 BP2 BP1 VDISP DP4/OR B1, C1, CONT 14 15 16 17 18 19 20
TC7129CPL
BUFF - 30 CREF + 29 CREF 28 COM 27 CONT 26 INT OUT 25 INT IN + 24 V 23 V - 22 LATCH/HOLD 21 DP3/UR B1, C1, CONT
A1, G1, D1
A1, G1, D1
44-Pin QFP
RANGE DGND OSC3 OSC1 OSC2 A.D. DP1 DP2 NC
RANGE
44-Pin PLCC
OSC3 OSC1 OSC2 A.D. DP1 DP2 NC
DGND
44 43
42
41 40 39
38
37
36
35
34
6
33 REF LO 32 REF HI 31 IN HI 30 IN LO 29 BUFF
5
4
3
2
1
44
43
42
41
40
6
39 REF LO 38 REF HI 37 IN HI 36 IN LO 35 BUFF 34 NC 33 CREF 32 CREF 31 COM 30 CONT 29 INT OUT
F1, E1, DP1 1 B2, C2, BATT 2 A2, G2, D2 3 F2, E2, DP2 4 B3, C3, MINUS 5 NC 6 A3, G3, D3 F3, E3, DP3
7
8
F1, E1, DP1 B2, C2, BATT A2, G2, D2
7 8 9
F2, E2, DP2 10 B3, C3, MINUS 11 NC 12 A3, G3, D3 13 F3, E3, DP3 14 B4, C4, BC5 15 A4, G4, D4 16 F4, E4, DP4 17
18 19 20 21 22 23 24
25
TC7129CKW
28 NC
- 27 CREF
26 C + REF 25 COM 24 CONT 23 INT OUT
TC7129CLW
-
+
7
B4, C4, BC5 9 A4, G4, D4 10 F4, E4, DP4 11
12 13 14 15 16 17 18 19 20 21 22
26
27
28
DP4/OR
BP1
DP3/UR
VDISP
LATCH/HOLD
DP4/OR
DP3/UR
VDISP
LATCH/HOLD
INT IN
INT IN
BP3
BP2
NC
V-
BP3
BP2
BP1
NC
V-
V+
V+
8
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
PIN DESCRIPTIONS
Pin No. 40-Pin TC7129CPL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Pin No. 44-Pin TC7129CKW
40 41 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19
Pin No. 44-Pin TC7129CLW
2 3 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25
Symbol
Function
Input to first clock inverter. Output of second clock inverter. Backplane square-wave output for driving annunciators. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Output to display segments. Backplane #3 output to display. Backplane #2 output to display. Backplane #1 output to display. Negative rail for display drivers. Input: When HI, turns on most significant decimal point. Output: Pulled HI when result count exceeds 19,999. Input: Second most significant decimal point on when HI. Output: Pulled HI when result count is less than 1000. Input: When floating, ADC operates in the free-run mode. When pulled HI, the last displayed reading is held. When pulled LO, the result counter contents aren shown inincrementing during the deintegrate phase of cycle. Output: Negative-going edge occurs when the data latches are updated. Can be used for converter status signal. Negative power supply terminal. Positive power supply terminal and positive rail for display drivers. Input to integrator amplifier. Output of integrator amplifier. Input: When LO, continuity flag on the display is OFF. When HI, continuity flag is ON. Output: HI when voltage between inputs is less than +200 mV. LO when voltage between inputs is more than +200 mV. Sets common-mode voltage of 3.2V below V + for DE, 10X, etc. Can be used as preregulator for external reference. Positive side of external reference capacitor. Negative side of external reference capacitor. Output of buffer amplifier. Negative input voltage terminal. Positive input voltage terminal.
OSC1 OSC3 ANNUNCIATOR B1, C1, CONT A1, G1, D1 F1, E1, DP1 B2, C2, LO BATT A2, G2, D2 F2, E2, DP2 B3, C3, MINUS A3, G3, D3 F3, E3, DP3 B4, C4, BC5 A4, D4, G4 F4, E4, DP4 BP3 BP2 BP1 VDISP DP4/OR DP3/UR LATCH/HOLD
23 24 25 26 27
20
26 27 28 29 30
V- V+ INT IN INT OUT CONTINUITY
21 23 24
28
25
31
COMMON
29 30 31 32 33
3-234
26 27 29 30 31
32 33 35 36 37
C+ REF C- REF BUFFER IN LO IN HI
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
PIN DESCRIPTIONS
Pin No. 40-Pin TC7129CPL
34 35 36 37 38 39 40
1
Pin No. 44-Pin TC7129CKW
32 33 34 35 36 37 38 6,17, 28, 39
Pin No. 44-Pin TC7129CLW
38 39 40 41 42 43 44 12, 23, 34,1
2
Symbol
REF HI REF LO DGND RANGE DP2 DP1 OSC2 NC
Function
Positive reference voltage in Negative reference voltage Internal ground reference for digital section. See "5V Power Supply" paragraph. 3 A pull-down for 200 mV scale. Pulled HI externally for 2V scale. Internal 3 A pull-down. When HI, decimal point 2 will be on. Internal 3 A pull-down. When HI, decimal point 1 will be on. Output of first clock inverter. Input of second clock inverter. No Connection
3 4
COMPONENT SELECTION (All pin designations refer to 40-Pin Dip)
The TC7129 is designed to be the heart of a highresolution analog measurement instrument. The only additional components required are a few passive elements, a voltage reference, an LCD, and a power source. Most component values are not critical; substitutes can be chosen based on the information given below. The basic circuit for a digital multimeter application is shown in Figure 1. See "Special Applications" for variations. Typical values for each component are shown. The sections below give component selection criteria. The resistor and capacitor values are not critical; those shown work for most applications. In some situations, the capacitor values may have to be adjusted to compensate for parasitic capacitance in the circuit. The capacitors can be low-cost ceramic devices. Some applications can use a simple RC network instead of a crystal oscillator. The RC oscillator has more potential for jitter, especially in the least significant digit. See "RC Oscillator."
5 6 7
Oscillator (XOSC, CO1, CO2, RO)
The primary criterion for selecting the crystal oscillator is to chose a frequency that achieves maximum rejection of line-frequency noise. To do this, the integration phase should last an integral number of line cycles. The integration phase of the TC7129 is 10,000 clock cycles on the 200 mV range and 1000 clock cycles on the 2V range. One clock cycle is equal to two oscillator cycles. For 60 Hz rejection, the oscillator frequency should be chosen so that the period of one line cycle equals the integration time for the 2V range: 1/60 second = 16.7 msec = 1000 clock cycles * 2 osc cycles/clock cycle , oscillator frequency giving an oscillator frequency of 120 kHz. A similar calculation gives an optimum frequency of 100 kHz for 50 Hz rejection.
Integrating Resistor (RINT)
The integrating resistor sets the charging current for the integrating capacitor. Choose a value that provides a current between 5 A and 20 A at 2V, the maximum fullscale input. The typical value chosen gives a charging current of 13.3 A: ICHARGE = 2V 13.3 A 150 k
Too high a value for RINT increases the sensitivity to noise pickup and increases errors due to leakage current. Too low a value degrades the linearity of the integration, leading to inaccurate readings.
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
LOW BATTERY
CONTINUITY V 5 pF +
CO1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DP4 /OR
21
VDISP CONTINUITY INT OUT INT IN V+
22 23 24 25 26 27
ANNUNC
OSC3
OSC1
DISPLAY DRIVE OUTPUTS
TC7129
REF HI IN LO IN HI
120 kHz
OSC2 DP1
CRYSTAL
COMMON
BUFFER
V- LATCH/ HOLD DP3 /UR
REF LO
RANGE
CREF- CREF+
29 30
DGND
DP2
28
31
32
33
34
35
36
37
38
39
40
330 k CINT 0.1 F CREF 1 f 150 k RINT
+ 9V
RO 10 pF + 0.1 F CIF RIF 100 k - V IN + RREF DREF 20 k CRF 0.1 F V+
CO2
TC04
10 k RBIAS
Figure 1.
Standard Circuit
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
Integrating Capacitor (CINT)
The charge stored in the integrating capacitor during the integrate phase is directly proportional to the input voltage. The primary selection criterion for CINT is to choose a value that gives the highest voltage swing while remaining within the high-linearity portion of the integrator output range. An integrator swing of 2V is the recommended value. The capacitor value can be calculated from the equation: tINT x IINT CINT = , VSWING where tINT is the integration time. Using the values derived above (assuming 60 Hz operation), the equation becomes: CINT = 16.7msec x 13.3 A = 0.1 F. 2V The capacitor should have low dielectric absorption to ensure good integration linearity. Polypropylene and Teflon capacitors are usually suitable. A good measurement of the dielectric absorption is to connect the reference capacitor across the inputs by connecting: Pin to Pin 20 33 (CREF+ to IN HI) 30 32 (CREF- to IN LO) A reading between 10,000 and 9998 is acceptable; anything lower indicates unacceptably high dielectric absorption.
1
Voltage Reference (DREF, RREF, RBIAS, CRF)
A TC04 band-gap reference provides a high-stability voltage reference of 1.25V. The reference potentiometer (RREF) provides an adjustment for adjusting the reference voltage; any value above 20 k is adequate. The bias resistor (RBIAS) limits the current through DREF to less than 150 A. The reference filter capacitor (CRF) forms an RC filter with RBIAS to help eliminate noise.
2 3 4 5 6 7
Input filter (RIF, CIF)
For added stability, an RC input noise filter is usually included in the circuit. The input filter resistor value should not exceed 100 k. A typical RC time constant value is 16.7msec to help reject line-frequency noise. The input filter capacitor should have low leakage for a high-impedance input.
Battery
The typical circuit uses a 9V battery as a power source. Any value between 6V and 12V can be used. For operation from batteries with voltages lower than 6V and for operation from power supplies, see "Powering the TC7129."
SPECIAL APPLICATIONS The TC7129 as a Replacement Part
The TC7129 is a direct pin-for-pin replacement part for the ICL7129. Note, however, that part requires a capacitor and resistor between pins 26 and 28 for phase compensation. Since the TC7129 uses internal phase compensation, these parts are not required and, in fact, must be removed from the circuit for stable operation.
Reference Capacitor (CREF)
The reference capacitor stores the reference voltage during several phases of the measurement cycle. Low leakage is the primary selection criterion for this component. The value must be high enough to offset the effect of stray capacitance at the capacitor terminals. A value of at least 1 F is recommended.
Powering the TC7129
While the most common power source for the TC7129 is a 9V battery, there are other possibilities. Some of the more common ones are explained below.
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
5V Power Supply
Measurements are made with respect to power supply ground. DGND (pin 36) is set internally to about 5V less than V+ (pin 24); it is not intended as a power supply input and must not be tied directly to power supply ground. (It can be used as a reference for external logic, as explained in "Connecting to External Logic." (See Figure 2.)
+5V
24 V+ REF HI 36 34
TC04
35 28 33 32
+
3.8V TO 6V
DGND REF LO COM
TC7129
IN HI
+
VIN
24 + V 0.1 F REF HI
8
34
2
IN LO V-
-
TC04
REF LO 35 28 33 32
3
+
10 F
23
TC7660
4 5
36 0.1 F
DGND
COM IN HI
10 F
+ VIN -
+
Figure 3. Powering the TC7129 From a Low-Voltage Battery
TC7129
0.1 F IN LO V- 23
+5V
-5V
Figure 2. Powering the TC7129 From a 5V Power Supply
24 V+ 0.1 F 35 36 0.1 F 33 DGND 28 34
Low-Voltage Battery Source
A battery with voltage between 3.8V and 6V can be used to power the TC7129 when used with a voltage-doubler circuit as shown in Figure 3. The voltage doubler uses the TC7660 DC-to-DC voltage converter and two external capacitors.
TC04
+
VIN
+5V Power Supply
Measurements are made with respect to power supply ground. COMMON (pin 28) is connected to REF LO (pin 35). A voltage doubler is needed, since the supply voltage is less than the 6V minimum needed by the TC7129. DGND (pin 36) must be isolated from power supply ground. (See Figure 4.)
8 V+ 2
TC7129
32 V-
-
+
10 F
23
TC7660
GND 3
4 5 10 F
Connecting to External Logic
External logic can be directly referenced to DGND (pin 36), provided that the supply current of the external logic does not exceed the sink current of DGND (Figure 5). A safe value for DGND sink current is 1.2 mA. If the sink current is expected to exceed this value, a buffer is recommended. (See Figure 6.)
3-238
+
Figure 4. Powering the TC7129 From a +5V Power Supply
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
V+
1
V +
2 3 4 5 6 7
24 EXTERNAL LOGIC
24 EXTERNAL LOGIC
TC7129
36 ILOGIC 23 V- DGND
- + ILOGIC 36
TC7129
DGND 23
V
Figure 5. External Logic Referenced Directly to DGND
-
Figure 6. External Logic Referenced to DGND With Buffer
Temperature Compensation
For most applications, VDISP (pin 19) can be connected directly to DGND (pin 36). For applications with a wide temperature range, some LCDs require that the drive levels vary with temperature to maintain good viewing angle and display contrast. Figure 7 shows two circuits that can be adjusted to give temperature compensation of about 10 mV/C between V+ (pin 24) and VDISP. The diode between DGND and VDISP should have a low turn-ON voltage because VDISP cannot exceed 0.3V below DGND.
V+
V+
1N4148
39 k 200 k 24
39 k 24
20 k
2N2222
TC7129
5 k + 36 75 k 23 - 19 VDISP 19
TC7129
VDISP 36 DGND 18 k 23
DGND
V-
V-
Figure 7.
Temperature Compensating Circuits
8
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
RC Oscillator
For applications in which 3-1/2 digit (100 V) resolution is sufficient, an RC oscillator is adequate. A recommended value for the capacitor is 51 pF. Other values can be used as long as they are sufficiently larger than the circuit parasitic capacitance. The resistor value is calculated from: R= 0.45 freq * C measurement of the time to ramp the integrated voltage to zero, and is therefore proportional to the input voltage being measured. This count can then be scaled and displayed as a measurement of the input voltage. Figure 9 shows the phases of the dual-slope conversion. The dual-slope method has a fundamental limitation. The count can only stop on a clock cycle, so that measurement accuracy is limited to the clock frequency. In addition, a delay in the zero-crossing comparator can add to the inaccuracy. Figure 10 shows these errors in an actual measurement.
For 120 kHz frequency and C = 51 pF, the calculated value of R is 75 k. The RC oscillator and the crystal oscillator circuits are shown in Figure 8.
Measuring Techniques
Two important techniques are used in the TC7129: successive integration and digital auto-zeroing. Successive integration is a refinement to the traditional dual-slope conversion technique.
INTEGRATE
DEINTEGRATE
ZERO CROSSING
Dual-Slope Conversion
A dual-slope conversion has two basic phases: integrate and deintegrate. During the integrate phase, the input signal is integrated for a fixed period of time; the integrated voltage level is thus proportional to the input voltage. During the deintegrate phase, the integrated voltage is ramped down at a fixed slope, and a counter counts the clock cycles until the integrator voltage crosses zero. The count is a
TIME
Figure 9. Dual-Slope Conversion
Successive Integration
The successive integration technique picks up where dual-slope conversion ends. The overshoot voltage shown in Figure 10, called the "integrator residue voltage," is measured to obtain a correction to the initial count. Figure 11 shows the cycles in a successive integration measurement. The waveform shown is for a negative input signal. The sequence of events during the measurement cycle is: Phase
INT1 DE1
TC7129
1 40 270 k 10 pF V+ 2
Description
Input signal is integrated for fixed time. (1000 clock cycles on 2V scale, 10,000 on 200 mV) Integrator voltage is ramped to zero. Counter counts up until zero crossing to produce reading accurate to 3-1/2 digits. Residue represents an overshoot of the actual input voltage. Rest; circuit settles. Residue voltage is amplified 10 times and inverted. Integrator voltage is ramped to zero. Counter counts down until zero crossing to correct reading to 4-1/2 digits. Residue represents an undershoot of the actual input voltage. Rest; circuit settles. Residue voltage is amplified 10 times and inverted. Integrator voltage is ramped to zero. Counter counts up until zero crossing to correct reading to 5-1/2 digits. Residue is discarded.
5 pF V+
120 kHz
REST X10 DE2
TC7129
1 40 75 k 51 pF 2
REST X10 DE3
Figure 8. Oscillator Circuits 3-240
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
1
INTEGRATE
DEINTEGRATE
2
OVERSHOOT DUE TO ZERO CROSSING BETWEEN CLOCK PULSES
TIME
INTEGRATOR RESIDUE VOLTAGE
3 4
CLOCK PULSES
OVERSHOOT CAUSED BY COMPARATOR DELAY OF 1 CLOCK PULSE
Figure 10.
Accuracy Errors in Dual-Slope Conversion
ZERO INTEGRATE AND LATCH
INT1 INTEGRATE
DE1 DEINTEGRATE
REST X10
DE2
REST
X10
DE3
ZERO INTEGRATE
5
TC7129
6
NOTE: Shaded area greatly expanded
in time and amplitude. INTEGRATOR RESIDUAL VOLTAGE
Figure 11. Integrator Waveform
Digital Auto-Zeroing
To eliminate the effect of amplifier offset errors, the TC7129 uses a digital auto-zeroing technique. After the input voltage is measured as described above, the measurement is repeated with the inputs shorted internally. The reading with inputs shorted is a measurement of the internal errors and is subtracted from the previous reading to obtain a corrected measurement. Digital auto-zeroing eliminates the need for an external auto-zeroing capacitor used in other ADCs. TELCOM SEMICONDUCTOR, INC.
Inside the TC7129
Figure 12 shows a simplified block diagram of the TC7129.
7
Integrator Section
The integrator section includes the integrator, comparator, input buffer amplifier, and analog switches used to change the circuit configuration during the separate measurement phases described earlier.
3-241
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
LOW BATTERY
CONTINUITY
SEGMENT DRIVES
BACKPLANE DRIVES ANNUNCIATOR DRIVE
OSC1 LATCH, DECODE DISPLAY MULTIPLEXER OSC2 VDISP
UP/DOWN RESULTS COUNTER OSC3 SEQUENCE COUNTER/DECODER
CONTROL LOGIC
RANGE L/H CONT V+ V- DGND
DP1 DP2 UR/DP3 OR/DP4 ANALOG SECTION REF HI REF LO
INT OUT
TC7129
INT IN
COMMON
IN IN HI LO
BUFF
Figure 12. 3-242
Functional Block Diagram
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
CREF REF HI REF LO RINT CINT
1
2
10 pF X10 COMPARATOR 1 + TO DIGITAL SECTION 100 pF - COMPARATOR 2
DE INT1 IN HI DE-
DE - + DE+ BUFFER
INTEGRATOR - +
COMMON INT1, INT2 IN LO
DE+
DE- INT REST
ZI, X10
3 4 5
- - CONTINUITY + V 200 mV +
500 k CONTINUITY COMPARATOR
TC7129
TO DISPLAY DRIVER Integrator Block Diagram
Figure 13.
Table I. Switch Legends Label
DE DE- DE+ INT1 INT2 INT REST ZI X10 X10
Meaning
Open during all deintegrate phases. Closed during all deintegrate phases when input voltage is negative. Closed during all deintegrate phases when input voltage is positive. Closed during the first integrate phase (measurement of the input voltage). Closed during the second integrate phase (measurement of the amplifier offset). Open during both integrate phases. Closed during the rest phase. Closed during the zero-integrate phase. Closed during the X10 phase. Open during the X10 phase.
- IN HI + BUFFER
COM
6
TC7129
- 200 mV 500 k TO DISPLAY DRIVER (NOT LATCHED) V +
IN LO
The buffer amplifier has a common-mode input voltage range from 1.5V above V- to 1V below V+. The integrator amplifier can swing to within 0.3V of the rails, although for best linearity the swing is usually limited to within 1V. Both amplifiers can supply up to 80 A of output current, but should be limited to 20 A for good linearity.
CONT
7
Figure 14.
Continuity Indicator Circuit
Continuity Indicator
A comparator with a 200 mV threshold is connected between IN HI (pin 33) and IN LO (pin 32). Whenever the voltage between inputs is less than 200 mV, the TELCOM SEMICONDUCTOR, INC.
CONTINUITY output (pin 27) will be pulled HIGH, activating the continuity annunciator on the display. The continuity pin can also be used as an input to drive the continuity annunciator directly from an external source. A schematic of the input/output nature of this pin is shown in Figure 15.
3-243
8
4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
Sequence and Results Counter
TC7129
500 k
DP4/OR, PIN 20 DP3/UR, PIN 21 LATCH/HOLD PIN 22 CONTINUITY, PIN 27
A sequence counter and associated control logic provide signals that operate the analog switches in the integrator section. The comparator output from the integrator gates the results counter. The results counter is a six-section up/ down decade counter which holds the intermediate results from each successive integration.
Overrange and Underrange Outputs
When the results counter holds a value greater than 19,999, the DP4/OR output (pin 20) is driven HIGH. When the results counter value is less than 1000, the DP3/UR output (pin 21) is driven HIGH. Both signals are valid on the falling edge of LATCH/HOLD (L/H) and do not change until the end of the next conversion cycle. The signals are updated at the end of each conversion unless the L/H input (pin 22) is held HIGH. Pins 20 and 21 can also be used as inputs for external control of decimal points 3 and 4. Figure 15 shows a schematic of the input/output nature of these pins.
Figure 15.
Input/Output Pin Schematic
Common and Digital Ground
The common and digital ground (DGND) outputs are generated from internal zener diodes. The voltage between V+ and DGND is the internal supply voltage for the digital section of the TC7129. Common can source approximately 12 A; DGND has essentially no source capability.
Low Battery
The low battery annunciator turns on when supply voltage between V+ and V- drops below 6.8V. The internal zener has a threshold of 6.3V. When the supply voltage drops below 6.8V, the transistor tied to V- turns OFF, pulling the "Low Battery" point HIGH. (See Figure 16.)
Latch/Hold
The L/H output goes LOW during the last 100 cycles of each conversion. This pulse latches the conversion data into the display driver section of the TC7129. This pin can also be used as an input. When driven HIGH, the display will not be updated; the previous reading is displayed. When driven LOW, the display reading is not latched; the sequence counter reading will be displayed. Since the counter is counting much faster than the backplanes are being updated, the reading shown in this mode is somewhat erratic.
24 12 A 3.2V 28 - N + LOGIC SECTION 36 P N 5V
V
+
Display Driver
COM
DGND
TC7129
23
Figure 16.
V
-
Digital Ground (DGND) and Common Outputs
The TC7129 drives a triplexed LCD with three backplanes. The LCD can include decimal points, polarity sign, and annunciators for continuity and low battery. Figure 17 shows the assignment of the display segments to the backplanes and segment drive lines. The backplane drive frequency is obtained by dividing the oscillator frequency by 1200. This results in a backplane drive frequency of 100 Hz for 60 Hz operation (120 kHz crystal) and 83.3 Hz for 50 Hz operation (100 kHz crystal). Backplane waveforms are shown in Figure 18. These appear on outputs BP1, BP2, BP3 (pins 16, 17, and 18). They remain the same regardless of the segments being driven. Other display output lines (pins 4 through 15) have waveforms that vary depending on the displayed values. Figure 19 shows a set of waveforms for the A, G, D outputs (pins 5, 8, 11, and 14) for several combinations of "ON" segments. TELCOM SEMICONDUCTOR, INC.
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4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS TC7129
LOW BATTERY CONTINUITY
1
2
BP1 BP2 BACKPLANE CONNECTIONS BP3
LOW BATTERY
CONTINUITY
3 4 5
VDD VH VL VDISP VDD VH VL VDISP VDD VH VL VDISP VDD VH
F4, E4, DP4 A4, G4, D4 B4, C4, BC4 F3, E3, DP3 A3, G3, D3 B3, C3, MINUS
B1, C1, CONTINUITY A1, G1, D1 F1, E1, DP1 B2, C2, LOW BATTERY A2, G2, D2 F2, E2, DP2
Figure 17.
Display Segment Assignments
BP1
b SEGMENT LINE ALL OFF
6 7
BP2
a SEGMENT ON d, g OFF
BP3
a, g ON d OFF
Figure 18.
Backplane Waveforms
ALL ON
The ANNUNCIATOR DRIVE output (pin 3) is a squarewave running at the backplane frequency (100 Hz or 83.3 Hz), with a peak-to-peak voltage equal to DGND voltage. Connecting an annunciator to pin 3 turns it ON; connecting it to its backplane turns it OFF. TELCOM SEMICONDUCTOR, INC.
VL VDISP
Figure 19.
Typical Display Output Waveforms 3-245
8

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